Signal integrity — why fast signals need a good layout.

The faster the edges, the more a trace behaves like a transmission line with its own physics. Whoever masters impedance, reflection and crosstalk builds reliable hardware.

Discuss PCB layout

What signal integrity means

Signal integrity (SI) describes how cleanly a signal travels along the trace. As frequency rises and edges become faster, effects appear that are negligible for slow signals: reflections, crosstalk, EMC and supply-voltage dips.

Controlled impedance

So that a signal is not reflected, the characteristic impedance must remain constant along the entire path. It results from trace width, spacing, height above the reference plane and the material. Typical targets are 50 Ω (single-ended) or 100 Ω (differential).

Reflections

At every impedance discontinuity — open line ends, stubs, missing termination — part of the signal is thrown back. This corrupts levels and timing.

Crosstalk

Closely adjacent lines couple interference into one another. A proven rule of thumb: keep the spacing between fast signals at least three times the trace width (the 3W rule).

Termination

With series or parallel termination matched to the characteristic impedance (e.g. 50 Ω on a 50-Ω line), reflections are effectively reduced.

SI and EMC belong together

Clean return-current paths and continuous ground planes improve signal integrity and EMC at the same time — see EMC-compliant layout. That is why we consider both together in the PCB layout.

Frequently asked questions

At what speed does signal integrity become important?

What matters is not the clock frequency alone but the edge rate (rise time). Even moderate clocks with very fast edges can create SI problems. When in doubt, account for it early in the layout.

Do I always need controlled impedance?

No — only for fast/critical signals (e.g. differential high-speed buses, clocked interfaces). We decide this per signal and align the layer stack-up accordingly.

Sources: Altium — High-Speed Signal Integrity, Cadence — Signal Integrity Challenges.